
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))

&soc {
	pil_gpu: qcom,kgsl-hyp {
		compatible = "qcom,pil-tz-generic";
		qcom,pas-id = <13>;
		qcom,firmware-name = "a650_zap";
	};

	msm_bus: qcom,kgsl-busmon {
		label = "kgsl-busmon";
		compatible = "qcom,kgsl-busmon";
		operating-points-v2 = <&gpu_opp_table>;
	};

	gpubw: qcom,gpubw {
		compatible = "qcom,devbw-ddr";
		governor = "bw_vbif";
		qcom,src-dst-ports = <26 512>;
		operating-points-v2 = <&suspendable_ddr_bw_opp_table>;
	};

	gpu_opp_table: gpu-opp-table {
		compatible = "operating-points-v2";

		opp-480000000 {
			opp-hz = /bits/ 64 <480000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;
		};

		opp-381000000 {
			opp-hz = /bits/ 64 <381000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;
		};

		opp-290000000 {
			opp-hz = /bits/ 64 <290000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
		};
	};

	msm_gpu: qcom,kgsl-3d0@3d00000 {
		label = "kgsl-3d0";
		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
		status = "ok";
		reg = <0x3d00000 0x40000>, <0x3d61000 0x800>,
			<0x3de0000 0x10000>, <0x3d8b000 0x2000>,
			<0x06900000 0x80000>;
		reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc",
				"isense_cntl", "qdss_gfx";
		interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "kgsl_3d0_irq";
		qcom,id = <0>;

		qcom,chipid = <0x06050000>;

		qcom,initial-pwrlevel = <2>;

		qcom,idle-timeout = <80>; /* msecs */

		qcom,no-nap;

		qcom,highest-bank-bit = <16>;

		qcom,min-access-length = <32>;

		qcom,ubwc-mode = <4>;

		qcom,snapshot-size = <0x200000>; /* bytes */

		qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */

		#cooling-cells = <2>;

		qcom,tzone-name = "gpuss-max-step";

		qcom,pm-qos-active-latency = <44>;

		clocks = <&clock_gpucc GPU_CC_CXO_CLK>,
			<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
			<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
			<&clock_gpucc GPU_CC_CX_GMU_CLK>,
			<&clock_gpucc GPU_CC_AHB_CLK>,
			<&clock_cpucc L3_GPU_VOTE_CLK>;

		clock-names = "rbbmtimer_clk", "mem_clk",
				"mem_iface_clk", "gmu_clk",
				"gpu_cc_ahb", "l3_vote";

		qcom,isense-clk-on-level = <1>;

		/* Bus Scale Settings */
		qcom,gpubw-dev = <&gpubw>;
		qcom,bus-control;

		/* GDSC regulator names */
		regulator-names = "vddcx", "vdd";
		/* GDSC oxili regulators */
		vddcx-supply = <&gpu_cx_gdsc>;
		vdd-supply = <&gpu_gx_gdsc>;

		/* GPU OPP data */
		operating-points-v2 = <&gpu_opp_table>;

		nvmem-cells = <&gpu_lm_efuse>, <&gpu_speed_bin>;
		nvmem-cell-names = "isense_slope", "speed_bin";

		qcom,bus-accesses-ddr7 = <970>;
		qcom,bus-accesses-ddr8 = <1162>;

		/* bus table */
		qcom,gpu-bus-table-0 {
			compatible = "qcom,gpu-bus-table",
				"qcom,gpu-bus-table-ddr7";
			qcom,msm-bus,name = "grp3d";
			qcom,msm-bus,num-cases = <12>;
			qcom,msm-bus,num-paths = <1>;
			qcom,msm-bus,vectors-KBps =
				<26 512 0 MHZ_TO_KBPS(0, 4)>,    /* index=0  */
				<26 512 0 MHZ_TO_KBPS(200, 4)>,  /* index=1  */
				<26 512 0 MHZ_TO_KBPS(300, 4)>,  /* index=2  */
				<26 512 0 MHZ_TO_KBPS(451, 4)>,  /* index=3  */
				<26 512 0 MHZ_TO_KBPS(547, 4)>,  /* index=4  */
				<26 512 0 MHZ_TO_KBPS(681, 4)>,  /* index=5  */
				<26 512 0 MHZ_TO_KBPS(768, 4)>,  /* index=6  */
				<26 512 0 MHZ_TO_KBPS(1017, 4)>, /* index=7  */
				<26 512 0 MHZ_TO_KBPS(1353, 4)>, /* index=8  */
				<26 512 0 MHZ_TO_KBPS(1555, 4)>, /* index=9  */
				<26 512 0 MHZ_TO_KBPS(1804, 4)>, /* index=10 */
				<26 512 0 MHZ_TO_KBPS(2092, 4)>; /* index=11 */
		};

		qcom,gpu-bus-table-1 {
			compatible = "qcom,gpu-bus-table",
				"qcom,gpu-bus-table-ddr8";
			qcom,msm-bus,name = "grp3d";
			qcom,msm-bus,num-cases = <12>;
			qcom,msm-bus,num-paths = <1>;
			qcom,msm-bus,vectors-KBps =
				<26 512 0 MHZ_TO_KBPS(0, 4)>,    /* index=0  */
				<26 512 0 MHZ_TO_KBPS(200, 4)>,  /* index=1  */
				<26 512 0 MHZ_TO_KBPS(300, 4)>,  /* index=2  */
				<26 512 0 MHZ_TO_KBPS(451, 4)>,  /* index=3  */
				<26 512 0 MHZ_TO_KBPS(547, 4)>,  /* index=4  */
				<26 512 0 MHZ_TO_KBPS(681, 4)>,  /* index=5  */
				<26 512 0 MHZ_TO_KBPS(768, 4)>,  /* index=6  */
				<26 512 0 MHZ_TO_KBPS(1017, 4)>, /* index=7  */
				<26 512 0 MHZ_TO_KBPS(1555, 4)>, /* index=8  */
				<26 512 0 MHZ_TO_KBPS(1804, 4)>, /* index=9  */
				<26 512 0 MHZ_TO_KBPS(2092, 4)>, /* index=10 */
				<26 512 0 MHZ_TO_KBPS(2736, 4)>; /* index=11 */
		};

		qcom,l3-pwrlevels {
			#address-cells = <1>;
			#size-cells = <0>;

			compatible = "qcom,l3-pwrlevels";

			qcom,l3-pwrlevel@0 {
				reg = <0>;
				qcom,l3-freq = <0>;
			};

			qcom,l3-pwrlevel@1 {
				reg = <1>;
				qcom,l3-freq = <864000000>;
			};

			qcom,l3-pwrlevel@2 {
				reg = <2>;
				qcom,l3-freq = <1344000000>;
			};
		};

		/* GPU Mempools */
		qcom,gpu-mempools {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "qcom,gpu-mempools";

			/* 4K Page Pool configuration */
			qcom,gpu-mempool@0 {
				reg = <0>;
				qcom,mempool-page-size = <4096>;
				qcom,mempool-reserved = <2048>;
				qcom,mempool-allocate;
			};
			/* 8K Page Pool configuration */
			qcom,gpu-mempool@1 {
				reg = <1>;
				qcom,mempool-page-size = <8192>;
				qcom,mempool-reserved = <1024>;
				qcom,mempool-allocate;
			};
			/* 64K Page Pool configuration */
			qcom,gpu-mempool@2 {
				reg = <2>;
				qcom,mempool-page-size = <65536>;
				qcom,mempool-reserved = <256>;
			};
			/* 1M Page Pool configuration */
			qcom,gpu-mempool@3 {
				reg = <3>;
				qcom,mempool-page-size = <1048576>;
				qcom,mempool-reserved = <32>;
			};
		};

		/* Power levels */
		qcom,gpu-pwrlevels {
			#address-cells = <1>;
			#size-cells = <0>;

			compatible = "qcom,gpu-pwrlevels";

			qcom,gpu-pwrlevel@0 {
				reg = <0>;
				qcom,gpu-freq = <480000000>;
				qcom,bus-freq-ddr7 = <11>;
				qcom,bus-min-ddr7 = <11>;
				qcom,bus-max-ddr7 = <11>;

				qcom,bus-freq-ddr8 = <11>;
				qcom,bus-min-ddr8 = <11>;
				qcom,bus-max-ddr8 = <11>;
			};

			qcom,gpu-pwrlevel@1 {
				reg = <1>;
				qcom,gpu-freq = <381000000>;
				qcom,bus-freq-ddr7 = <9>;
				qcom,bus-min-ddr7 = <7>;
				qcom,bus-max-ddr7 = <11>;

				qcom,bus-freq-ddr8 = <8>;
				qcom,bus-min-ddr8 = <7>;
				qcom,bus-max-ddr8 = <11>;
			};

			qcom,gpu-pwrlevel@2 {
				reg = <2>;
				qcom,gpu-freq = <290000000>;
				qcom,bus-freq-ddr7 = <2>;
				qcom,bus-min-ddr7 = <1>;
				qcom,bus-max-ddr7 = <9>;

				qcom,bus-freq-ddr8 = <2>;
				qcom,bus-min-ddr8 = <1>;
				qcom,bus-max-ddr8 = <8>;
			};

			qcom,gpu-pwrlevel@3 {
				reg = <3>;
				qcom,gpu-freq = <0>;
				qcom,bus-freq = <0>;
				qcom,bus-min = <0>;
				qcom,bus-max = <0>;
			};
		};
	};

	kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
		compatible = "qcom,kgsl-smmu-v2";

		reg = <0x03da0000 0x10000>;
		/* CB5(ATOS) & CB5/6/7 are protected by HYP */
		qcom,protect = <0xa0000 0xc000>;

		clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
			<&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
			<&clock_gpucc GPU_CC_AHB_CLK>;
		clock-names = "gcc_gpu_memnoc_gfx",
			"gcc_gpu_snoc_dvm_gfx",
			"gpu_cc_ahb";

		qcom,secure_align_mask = <0xfff>;
		qcom,retention;
		qcom,hyp_secure_alloc;

		gfx3d_user: gfx3d_user {
			compatible = "qcom,smmu-kgsl-cb";
			label = "gfx3d_user";
			iommus = <&kgsl_smmu 0x0 0x401>;
			qcom,iommu-dma = "disabled";
			qcom,gpu-offset = <0xa8000>;
		};

		gfx3d_secure: gfx3d_secure {
			compatible = "qcom,smmu-kgsl-cb";
			label = "gfx3d_secure";
			iommus = <&kgsl_smmu 0x2 0x400>;
			qcom,iommu-dma = "disabled";
		};
	};

	gmu: qcom,gmu@3d6a000 {
		label = "kgsl-gmu";
		compatible = "qcom,gpu-gmu";

		reg = <0x3d6a000 0x30000>,
			<0xb290000 0x10000>,
			<0xb490000 0x10000>;
		reg-names = "kgsl_gmu_reg",
			"kgsl_gmu_pdc_cfg",
			"kgsl_gmu_pdc_seq";

		interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
						<0 305 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";

		qcom,msm-bus,name = "cnoc";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<26 10036 0 0>,		/* CNOC off */
			<26 10036 0 100>;	/* CNOC on */

		regulator-names = "vddcx", "vdd";
		vddcx-supply = <&gpu_cx_gdsc>;
		vdd-supply = <&gpu_gx_gdsc>;

		clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>,
				<&clock_gpucc GPU_CC_CXO_CLK>,
				<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
				<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
				<&clock_gpucc GPU_CC_AHB_CLK>;

		clock-names = "gmu_clk", "cxo_clk", "axi_clk",
				"memnoc_clk", "gpu_cc_ahb";

		/* AOP mailbox for sending ACD enable and disable messages */
		mboxes = <&qmp_aop 0>;
		mbox-names = "aop";

		gmu_user: gmu_user {
			compatible = "qcom,smmu-gmu-user-cb";
			iommus = <&kgsl_smmu 0x4 0x400>;
			qcom,iommu-dma = "disabled";
		};

		gmu_kernel: gmu_kernel {
			compatible = "qcom,smmu-gmu-kernel-cb";
			iommus = <&kgsl_smmu 0x5 0x400>;
			qcom,iommu-dma = "disabled";
		};
	};
};
